It is known that the sum of sine waves of equal amplitudes but of fixed phase difference between each member is:
            ∑      0              n        -        1              ⁢                  ⁢          ⅇ              j        ⁡                  (                      wt            +                          n              ⁢                                                          ⁢              Δ              ⁢                                                          ⁢              ϕ                                )                      =                    sin        ⁡                  (                                    (                              n                ⁢                                                                  ⁢                Δ                ⁢                                                                  ⁢                ϕ                            )                        /            2                    )                            sin        ⁡                  (                                    (              Δϕ              )                        /            2                    )                      ⁢          ⅇ              j        ⁢                                  ⁢        ω        ⁢                                  ⁢        t            where ΔΦ is the phase difference between the members which can be visualized as vectors. This sum can be formed from the input to a transmitter by adding inputs phase shifted by ΔΦ to the input as shown in FIGS. 1A, 1B and 1C. We assume here that the signal input, ejωt are configured to sum with the amplitude in each path (branch).
In FIG. 1A, Item 1 is a channel filter allowing a band of frequencies to be received and supplied to the summer 2. The output of the summer is phase shifted in 3, which is a phase shifting device the phase shift of which is a function of frequency. The output of 3 is switched on or off by 4 in accordance with a control signal which may be data or timing bits. The switch output is fed back to the summer 2 and adds to the input in a phased manner as shown in vector form in FIG. 1B. That figure assumes there is no time delay around the loop.
If now the ΔΦ's in the branches (paths) are made functions of the frequencies of input signals in the same manner as was done in the transmitter, the paths are independently responsive to the incoming signals according to their frequencies. Thus, an incoming group of signals to the sender is enhanced by the arrangement of FIG. 1A. The input signals remain substantially unchanged during this summing. For ΔΦ=0 the output is n=60 but for ΔΦ greater than π/n the magnitude is close to 0. A resulting plot for n=60 is shown in FIG. 1C. This plot shows that for. ΔΦ=0 the output is n=60 but for ΔΦ greater than π/n the magnitude is close to 0. Thus, a group of such paths phase shifted 2π/n from each other not typically interfere with each other. A switched phase inverter is connected to each independent phase path to control the built up signals in each path by inserting a 180° phase shift under the control of an information bit. When this is done, the summer becomes a subtractor and eliminates signal from that path. FIG. 2 shows such an arrangement for sending such bit controlled incremental phased signals.
The system consists of a transmit and receive location in each of which there are several branches. Phase shifters 101a . . . 101n are located in each of the transmit station branches. Each of these phase shifts ΔΦ1, ΔΦ2, . . . ΔΦn, varies distinctively with frequency. Switched Inverters 103, 103a . . . 103n are also in the respective branches. These switches are responsive to control signals from coder 100 which supplies different digital control pulse sequences to the individual branches. These switches may invert the phase of the branch signal, as stated above, or simply turn the branch on and off in accordance with the control signal. The timing is controlled by the clock 102. The outputs of all the branches are supplied to an adder 200 which also receives a band of signals from filter 106. This band of signals, Σ1 cos ω1 t, Σ2 cos ω2 t, . . . Σn cos ωn t, may originate from noise or a return path from the receiver.
Filter 114 represents the transmission channel bandpass. A group of frequencies selected by the transmitter process is supplied to adder 205, which sums this input with all of the outputs of the receiver branches. The output of 205 goes to all of the branches. Phase shifters 116, 116a . . . 116n are similar to 101, 101a . . . 101n and provide corresponding phase shifts for the same frequency of the corresponding transmitter branch. Units 140, 140a, . . . 140n limit the build up of signal in the branches. This is done by opening the channel for bit length periods only controlled by clock 102a. Bits are detected by amplitude detectors 130, 130a, . . . 130n when the built-up signals exceed a threshold. As shown in FIG. 2, gates 132, 132a, . . . , 132n enable signal flow to respective amplitude detectors 130, 130a, . . . , 130n while enabling simultaneous control of limiting units 140, 140a, . . . , 140n in accordance with the clock 102a. Clocks 102 and 102a are synchronized. Amplifier 115 may be used to offset transmission loss between receiver and transmitter.
FIG. 3 shows the operation of the oversampled digital spike bandpass filter. Each symbol (1 MHz symbol rate) received from the transmission channel is gated and used as the input to the spike bandpass filter. The gated symbol stored in buffer 351 is repeatedly clocked out at 100 MHz rate. That is, the repeated symbols appear at an oversampled symbol rate of 100 MHz at the input of the digital spike filters 352 and 352A. The last symbol of the output of the digital filters after a stable symbol recovery are gated out and the last noise symbol of 352A is subtracted from the signal plus noise symbol in summing amplifier 353 and stored in buffer 354. The stable output appears at the end of 1 microsecond. The samples in the symbol are then read out at 1 MHz rate from buffer 354, which is the symbol rate received from the sending side. This signal Y(t) is used as the input to counter 308 and computer 309 to develop DVx and Dvy components. The operation of the spike filters is entirely the same as previously described except that the noise filter 352A is tuned 1 kHz from the signal filter 352.
A simpler oversampled digital spike filter may be employed than the standard FIR. As shown in FIG. 4, it consists of a single delay unit 355. The output of the delay unit 355 is summed in adder 356 with the input so that the output is:
En=en sin ωt+en−1(wt+τ0) where τ0 is the delay of unit 355. This signal is fed back to adder 357 where it adds to the incoming signal e. The successive summation after n iterations results in En=(sin n ωto/sin ωto)ejωto, where ω=2πf. When f=fo, 2πfo, π0=2π,the magnitude of En will=n, the maximum value, and the nulls occur at frequencies n±fo2n from fo which defines the bandwidth of the filter. Thus, this system is a narrow pass filter. A filter tuned to the null frequency of 355 provides the noise subtracting signal. This filter is composed of delay 355A and adders 356A and 357A. Subtraction takes place in summation amplifier 358. However, the circuit shown in FIG. 4 has an inherent disadvantage in that the sampling rate is limited by the Q of the analog resonant circuit.